MOBILESINDIA: RAMBUS Mobile Memory Initiative

Squeezing big performance into tiny packages
System-in-Package (SiP) technology stacks a number of integrated circuits - such as a media processor, DRAM, and Flash memory device - in a single package or module. SiP allows designers to achieve high functionality in a very compact space making it ideal for mobile phones. Though it offers great benefits, SiP faces a big challenge: the difficulty in determining whether memory devices are known good die (KGD) before assembly of the SiP. This can lead to poor manufacturing yields and increased costs. Thanks to Rambus innovations, available for licensing, technology such as SiPFLOW™ can address the KGD challenge achieving assembly yields of better than 100 defective parts per million devices (DPPM). That means designers can squeeze more performance into mobile phones at a price that consumers will like.

Enabling a new generation of media-rich mobile products
Consumers will come to expect the High Definition (HD) experience of the living room from the mobile devices they carry everyday. In addition, they'll want features including HD resolution video recorders, multi-megapixel digital still cameras, 3D games, and media-rich web applications. These advanced mobile devices will be capable of encoding and transmitting high definition content directly to HDTVs, home PCs and servers. To pack all that functionality in a form factor that's thin, light and delivered with a pleasing aesthetic presents a tremendous challenge for mobile device designers. Chief among these challenges will be the development of a high-performance memory architecture that meets the power efficiency constraints of battery-operated products.

The Rambus Mobile Memory Initiative pioneers high-bandwidth, low-power memory signaling technologies that can meet the needs of future smartphones, netbooks, and mobile gaming and multimedia products. Technologies developed through the Mobile Memory Initiative will enable future mobile memory architectures capable of achieving data rates of 4.3 gigabits per second (Gbps) at best-in-class power efficiency. With this performance, designers can realize more than 17 Gigabytes per second (GB/s) of memory bandwidth from a single mobile DRAM device.

Breakthrough innovations achieve performance and power efficiency
To achieve a high-bandwidth, low-power memory interface solution, Rambus has developed breakthrough innovations that include:

Very Low-Swing Differential Signaling (VLSD) - combines the robust signaling qualities of a differential architecture with innovative circuit techniques to greatly reduce active power consumption;

FlexClocking™ Architecture - a clock-forwarded and clock-distributed topology, enables high-speed operation and a simplified DRAM interface; and

Advanced Power State Management (APSM) - in conjunction with the FlexClocking architecture, provides fast switching times between power-saving modes and delivers optimized power efficiency across a diverse range of usage profiles.
These innovations and others developed by Rambus through the Mobile Memory Initiative, will provide the foundation for a future mobile memory architecture that offers increased performance, high bandwidth, and superior power efficiency.

Rambus' Very Low-Swing Differential Signaling combines the robust signaling qualities of a differential architecture, demonstrated in our Low Power Initiative, with innovative circuit techniques to minimize power consumption. Using a ground reference voltage mode driver, VLSD enables data rates of up to 4.3Gbps with only a 200mV peak-to-peak differential voltage swing and a common mode of 100mV.

The Rambus Mobile Memory Initiative also showcases the FlexClocking Architecture. FlexClocking architecture is a topology where the clock is forwarded and distributed to both the controller and the DRAM device from a central PLL. Using Rambus FlexPhase™ technology to adjust for any variability between the clock and DQ signals, the FlexClocking Architecture enables high-speed operation without the need for a DLL or PLL on the DRAM device. This simplifies DRAM design and reduces power consumption.


The FlexClocking™ Architecture enables high performance and simplified mobile DRAM design

The third featured innovation of the Mobile Memory Initiative, Advanced Power State Management, builds on the FlexClocking Architecture and innovative circuit design techniques. Advanced Power State Management (APSM) reduces memory system power, optimizes power efficiency across operating modes, and provides ultra-fast transition times between various low-power and active operating modes.

With VLSD, FlexClocking Architecture, APSM and other innovations to be developed through the Mobile Memory Initiative, Rambus provides the foundation technologies for achieving data rates of 4.3Gbps at best-in-class power efficiency. With this level of performance, designers can realize more than 17GB/s of memory bandwidth from a single mobile DRAM device. Through the Mobile Memory Initiative and the architectural solutions that follow, Rambus enables its customers to develop the memory solutions for a new generation of smartphones, mobile gaming, and mobile multimedia products that will enrich the lives of consumers worldwide.

Rambus innovations in today's Mobile Memory
Current generation smart phones offer a rich array of features including email, web browsing, games, music and movies. Making these features possible requires innovations which deliver superior performance and are tailored to the low-power environment of battery operated mobile devices. Mobile memory solutions, such as LPDDR memory, are no exception. Numerous Rambus patented innovations, including many that have already been proven in computer and graphics applications, enable low-power solutions essential to today's mobile applications and are available for licensing.